1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for forming a single diffusion break between finFET devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epitaxial (epi) semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device, or the recesses may be overfilled, thus forming raised source/drain regions. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called finFET device has a three-dimensional (3D) structure. FIG. 1A is a side view of an illustrative prior art finFET semiconductor device 100 that is formed above a semiconductor substrate 105. In this example, the finFET device 100 includes three illustrative fins 110, a gate structure 115, sidewall spacers 120, and a gate cap 125. The gate structure 115 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 100. The fins 110 have a three-dimensional configuration. The portions of the fins 110 covered by the gate structure 115 is the channel region of the finFET device 100. An isolation structure 130 is formed between the fins 110. In a conventional process flow, the portions of the fins 110 that are positioned outside of the spacers 120, i.e., in the source/drain regions of the device 100, may be increased in size or even merged together by performing one or more epitaxial growth processes. The process of increasing the size of the fins 110 in the source/drain regions of the device 100 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions.
A particular fin 110 may be used to fabricate multiple devices. FIG. 1B illustrates a cross-sectional view of the finFET device 100 along the length of one fin 110 prior to the formation of any gate structures 115. One or more diffusion breaks 135, 140 are formed along the axial length of the fin 110 to define separate fin portions by removing a portion of the fin 110 and replacing it with a dielectric material. The strength of the isolation provided by the diffusion break 135, 140 depends on its size. A diffusion break having a lateral width (in the current transport direction, or gate length (GL) direction of the completed devices) corresponding to the lateral width of two adjacent gate structures 115 (later formed) is referred to as a double diffusion break 135, and a diffusion break having a lateral width corresponding to the lateral width of one gate structure 115 is referred to as a single diffusion break 140. The process for forming the single diffusion break gouges the fin 110 and defines recesses 145.
FIG. 1C illustrates the device 100 after a plurality of processes were performed to define a plurality of gate structures 115, with cap layers 125, and sidewall spacers 120 above the fin 110. FIG. 1D illustrates the device 100 after a self-aligned etch process was performed to recess the fin 110 using the gate structures 115 and spacers 120 as an etch mask to define recesses 150, 155 in the fin 110. Because of the fin gouging, the recesses 150 adjacent the single diffusion break 140 are deeper than the other recesses 155.
FIG. 1E illustrates the device 100 after an epitaxial growth process was performed to define epitaxial regions 160, 165 in the recesses 150, 155. Due to the difference in the depth of the recesses 150, 155, the post-fill height of the epitaxial region 160 is less than that of the epitaxial region 165. This epitaxial material underfill changes the electrical characteristics of the device 100 in the region adjacent to the single diffusion break 140 as compared to the regions without underfill.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.